The present invention relates to digital clock synthesis, and more particularly to direct synthesis of a digital audio sample clock based upon any standard digital video sample frequency for video time scale accurate audio recording without using a phase locked loop.
There is a frequency drift between nominal audio and video reference frequencies, generally on the order of 10 to 100 parts per million (ppm), and there is an audio/video synchronization problem caused by the actual one part per thousand fractional sample rate offset of 525 line/60 Hz video relative to its nominal 60 Hz field rate, i.e., 60.0 Hz .sup.* 1000/1001 or 59.9400599400 Hz. A phase locked loop (PLL) often is used between audio and video to compensate for frequency drift between nominal reference frequencies. Any differential frequency drift causes time scale drift between the audio and video, known generally as "lip sync" error. To maintain lip-sync, audio and video time scales need to track within the order of 10 milliseconds (ms). A 100 ppm frequency drift, regardless of nominal audio sample frequency, results in a 10 ms time scale drift within only 100 seconds.
As described in co-pending U.S. patent application Ser. No. 08/096,356 filed Jul. 23, 1993 by Michael Poimboeuf et al entitled "Synchronization of Digital Audio with Digital Video" incorporated herein by reference, there are a fractional number of 32 KHz, 44.1 KHz or 48 KHz audio samples, i.e., 533.867, 735.735 and 800.8 respectively, in the time span of one 525/60 video field. The smallest number of video fields which contain an integer number of audio samples for these rates, or minimum field denominator (mfd), are 15 (8008 samples), 200 (147147 samples) and 5 (4004) respectively. These minimum number of samples represent the minimum sample quotient (msq) for each respective field denominator. These ratios make N to M matching, where N and M are any integers, between audio and video sampling frequencies difficult to accomplish.
Prior techniques have used the following methods:
1. Reducing the sample rate by one part per thousand, phase locking that audio sample rate to the 525/60 video sample frequency, rounding up the published rate by not publishing enough significant digits to show error, and calling that rate "synchronized to video" so that 44.056 . . . KHz becomes 44.1 KHz and 47.952 . . . KHz becomes 48 KHz. This method is misleading to the consumer and incompatible with ANSI standard sample rates; PA1 2. Blocking the audio data into unequal blocks of audio and phase locking that audio sample rate to the video sample rate, i.e., digital video tape recorders format data into a 5 frame (10 field) sequence using multiple, unequal audio blocks of 160 and 161 samples, which requires a separate linear control track containing the frame sequence and is sub-optimal for field based disk recording (Watkinson, "The Art of Digital Audio", ISBN 0 240 5 1270 7, Focal Press 1988, pgs. 393-394); PA1 3. Resampling using interpolation/decimation, and/or polyphase sample rate conversion, combined with phase locked loops, and/or sample buffers (Watkinson supra, pg. 546); and PA1 4. "Stutter skip" synchronization, per the above-mentioned patent application, which relies upon "sample stuffing" using excess channel bandwidth and phase locked loops to control frequency drift.
What is desired is a method for direct synthesis of a digital audio sample clock for recording digital audio sampled at any frequency, including ANSI S4.28-1984 (AESS) and MPC (Microsoft Press "Multimedia PC Specification Version 1.0 1992), together with digital video sampled at 525/60 and 625/50 CCIR frequencies (ANSI S4.40-1992 (AES3)).